TTL circuits are derived from a common NAND logic structure of which FIG. 1 shows a conventional arrangement. In this TTL gate, a set of logical input voltage signals represented here by input voltages V.sub.I1, V.sub.I2, and V.sub.I3 are provided to the corresponding emitters of a multiple-emitter NPN input transistor Q1. Its collector is connected to the base of an NPN phase-splitting drive transistor Q2 in a switching section of the gate.
The connection of the Q1 collector to the Q2 base was originally the distinguishing feature of TTL circuitry. More recently, the definition of TTL has loosened somewhat. TTL today generally means a family of bipolar devices having certain input/output characteristics. The internal circuitry of current TTL gates may contain some circuitry that would strictly fall in another logic family such as diode transistor logic, integrated injection logic, and the like. Even the Q1 collector-Q2 base connection may be absent as long as the necessary input/output conditions are satisfied within the general realm of TTL design.
Returning to FIG. 1, the Q1 base is connected to a current source consisting of a resistor R1 connected to a source of a high supply voltage V.sub.CC. The Q2 collector is connected to a current source formed by a resistor R2 tied to the V.sub.CC supply. The Q2 collector is further connected to the base of an NPN level-shifting transistor Q3. Its emitter drives an NPN output pull-up transistor Q4 and is also coupled through a resistor R3 to the Q4 emitter. The interconnected collectors of the Darlington pair Q3 and Q4 are connected to a current source consisting of a resistor R4 tied to the V.sub.CC supply.
The Q2 emitter is connected by way of a line 10 to the base of an NPN output pull-down transistor Q5 whose emitter is connected to a source of a low supply voltage V.sub.EE. A logical output voltage signal V.sub.O is provided from the interconnection of the Q5 collector and the Q4 emitter. A passive output pull-down circuit 12 consisting here of a resistor R5 is connected between the V.sub.EE supply and the Q5 base by way of line 10.
The operation of this TTL gate can be understood by first assuming that each of digital inputs V.sub.I1 -V.sub.I3 is at a high value or logical "1" (hereafter usually just "1") above the input switching point. Transistor Q1 has its base-collector junction conductively forward biased. This enables the R1 current source to provide current through the Q1 base-collector junction to the base of drive transistor Q2 so as to make it conductive. The R2 current source provides current through transistor Q2 to the base of transistor Q5 which is likewise turned on. Transistors Q3 and Q4 are turned off because the Q2 collector is at a low voltage. Output voltage V.sub.O is at a low value or logical "0" (hereafter usually just "0").
At least one of voltages V.sub.I1 -V.sub.I3 is now dropped to a "0" below the input switching point so as to conductively forward bias the corresponding Q1 base-emitter junctions(s). This causes transistor Q2 to turn off which, in turn, causes transistor Q5 to turn off. The Q2 collector goes to a high voltage, causing transistor Q3 to turn on. Transistor Q4 then turns on and actively pulls voltage V.sub.O up to a "1". The reverse occurs when all of input voltages V.sub.I1 -V.sub.I3 at "0" are raised to "1". The R1 source again provides current to the base of transistor Q2, enabling it to turn on. Its collector voltage goes low, forcing transistors Q3 and Q4 to turn back off. The turning on of transistor Q2 causes transistor Q5 to turn on and actively pull digital output V.sub.O down to "0".
In this type of TTL gate, pull-down circuit 12 provides a discharge path between the Q5 base and the V.sub.EE supply for removing the charge existing in the Q5 base when output V.sub.O goes high. This turns output transistor Q5 off faster so as to decrease the low-to-high output switching time. FIG. 1 illustrates perhaps the simplest such discharge path in the form of resistor R5. The difficulty with resistor R5 is that it draws a substantial amount of current from the V.sub.CC supply when output V.sub.O is low. Typically, resistor R5 draws about one third to one half of the current from the R2 source, the remainder of the R2 current going to transistor Q5. In turn, the R2 current is typically 80%-90% of the total current I.sub.CCL provided from the V.sub.CC supply when output V.sub.O is low. Inasmuch as I.sub.CCL is normally much greater than the total current I.sub.CCH provided from the V.sub.CC supply when output V.sub.O is high, the R5 current is a significant drain on an integrated circuit containing the gate of FIG. 1.
FIG. 2 shows another version of pull-down circuit 12 employable in the gate of FIG. 1. In FIG. 2, a Schottky diode D1 is connected between resistor R5 and the V.sub.EE supply. When transistor Q5 is turned on, diode D1 is forwardly conductive and transmits current from the R2 source to the V.sub.EE supply. This occurs because the Q5 V.sub.BE is greater than the voltage of about a V.sub.SH across diode D1. V.sub.BE is the base-to-emitter voltage for a bipolar transistor when its base-emitter junction is just conductively forward biased. V.sub.SH, which is about 0.25 volt less than a standard V.sub.BE for an NPN transistor, is the standard Schottky diode-drop voltage for a Schottky diode when it is just conductively forward biased. When transistor Q5 turns off, diode D1 remains on to discharge the base of transistor Q5 until its base-to-emitter voltage drops just below 1V.sub.SH Diode D1 then turns off so as to effectively prevent the Q5 base from dropping further. The Q5 base only has to rise slightly more than the difference between the Q5 V.sub.BE and 1V.sub.SH when transistor Q5 turns back on. This decreases the high-to-low output switching time compared to FIG. 1 in which the Q5 base travels the full Q5 V.sub.BE. However, the I.sub.CCL of circuit 12 of FIG. 2 is approximately equal to the high value of FIG. 1. This is again disadvantageous.
FIG. 3 illustrates another version of pull-down circuit 12 suitable for the gate of FIG. 1. In circuit 12 of FIG. 3 as disclosed in U.S. Pat. No. RE 27,804, an NPN transistor Q6 is collector-emitter connected between resistor R5 and the V.sub.EE supply. The Q6 base is coupled through a resistor R6 to the Q5 base. The effective V.sub.BE of transistor Q6 is less than that of output transistor Q5. As a result, transistor Q6 turns off in response to transistor Q5 turning off and vice versa. Just before transistor Q6 turns off, it provides a path to the V.sub.EE supply for discharging the Q5 base. Transistor Q6 subsequently allows the base of transistor Q5 to drop only slightly below its turn-on point. This further decreases the high-to-low output switching time. However, an undesirable ripple in output V.sub.O may occur just as transistor Q5 turns off. Moreover, circuit 12 of FIG. 3 has the same disadvantage as circuits 12 of FIGS. 1 and 2 in that it draws an undesirably high amount of current from the V.sub.CC supply when voltage V.sub.O is low.